The present invention relates to a phase change memory device, and more particularly, to a phase change memory device in which a phase change layer can be formed in a stable manner.
Memory devices are typically divided into two categories: volatile random access memory (RAM), which loses inputted information when power is interrupted; and non-volatile read-only memory (ROM), which continuously maintains the stored state of inputted information even when power is interrupted. Examples of volatile RAM include dynamic RAM (DRAM) and static RAM (SRAM), and examples of non-volatile ROM include flash memory devices such as electrically erasable and programmable ROM (EEPROM) can be mentioned.
Although DRAM is an excellent memory device, DRAM must have a high charge storing capacity, and therefore the surface area of an electrode of the DRAM must be increased. When the surface area of the electrode is increased, high levels of integration become difficult. Further, in flash memory devices two gates are stacked upon one another. Accordingly, a high operation voltage is required. Therefore, the power source voltage becomes insufficient, and a separate booster circuit is necessary to supply the required voltage for write and delete operations. This also makes it difficult to accomplish high levels of integration.
In order to rectify these problems, attempts have been made to develop a memory device having a simple configuration that is capable of accomplishing a high level of integration while retaining the characteristics of a non-volatile memory device. As a result, phase change memory devices are currently being studied.
FIG. 1 is a cross-sectional view showing a conventional phase change memory device.
In FIG. 1, a bottom electrode 110 is formed on a semiconductor substrate 100 having a switching element (not shown). An insulation layer 120 is formed over the semiconductor substrate 100 to cover the bottom electrode 110. A contact plug 130 is formed in the insulation layer 120 to contact the bottom electrode 110. A stacked pattern consisting of a phase change layer 150 and a top electrode 160 is formed on the contact plug 130 and the insulation layer 120 contacts the contact plug 130.
In a phase change memory device, a phase change occurs in the phase change layer 150 (which is interposed between the bottom and top electrodes 110 and 160) from a crystalline state to an amorphous state due to a current flow between the bottom electrode 110 and the top electrode 160. There resistance of the crystalline state is different from that of the amorphous state, and information stored in a cell is recognized based on this difference.
The phase change memory device has a simple configuration and can be highly integrated since there is no interference between adjoining cells. The phase change memory device can operate at high speeds, since the phase change memory device has a rapid read speed (several tens of ns) and a relatively rapid write speed (several tens to several hundreds of ns). Also, the phase change memory device has excellent compatibility with existing CMOS logic processes; and therefore, manufacturing cost can be saved. Accordingly, phase change memory devices are looked upon as a memory device with a high degree commercial potential.
However, in the conventional phase change memory device described above, the phase change layer formed on the insulation layer is formed as an unstable thin film. Therefore, a problem exists, in that there is a high probability that the phase change layer will peel off of the bottom electrode during a subsequent patterning process.
In more detail, in a typical phase change memory device, a chalcogenide layer as a compound composed of germanium (Ge), antimony (Sb) and tellurium (Te) is used as the phase change material. The adhesion of the chalcogenide layer and the insulating material is unstable, and therefore the chalcogenide layer cannot be uniformly formed as a thin film on the insulating material. As a consequence, the chalcogenide layer peels off of the bottom electrode during a subsequent patterning process.
FIG. 2 includes photographs showing thin film characteristics of a chalcogenide layer formed as a phase change layer on a metallic material and an insulating material.
When viewing FIG. 2, one can see that when the chalcogenide layer is formed on a TiN or W metal layer, the chalcogenide layer is formed as a thin film having dense grains. On the other hand, one can see that when the chalcogenide layer is formed on an SiO2 or an Si3N4 insulating layer, the chalcogenide layer cannot be formed as a thin film having dense grains due to the growth of non-uniform grains.
As a consequence, in the conventional phase change memory device, the phase change layer can peel off of the bottom electrode due to a poor adhesion force between the insulating material and the phase change layer, and therefore the phase change layer cannot be formed in a stable manner. Accordingly, it is difficult to ensure the characteristics and reliability of the conventional phase change memory device.